1. Technical Field
The present invention relates to an address generator that generates addresses indicating line positions of a photoelectric conversion element, which are objects of readout processing or reset processing for accumulated charges in an image capturing device, and an image capturing device including the address generator.
2. Related Art
As solid-state imaging devices, there are an image sensor of a CCD (Charge Coupled Device) type (hereinafter referred to as CCD sensor) and an image sensor of a CMOS type (hereinafter referred to as CMOS sensor). There is also proposed a MOS solid-state imaging device of a threshold voltage modulation system (hereinafter referred to as substrate modulation type sensor) that realizes both a high image quality and low power consumption. The CMOS sensor and the substrate modulation type sensor (hereinafter referred to as CMOS sensor and the like) have been actively developed in recent years because of advantages such as power consumption and process cost lower than those of the CCD sensor.
The CMOS sensor and the like have a rolling shutter mode for performing processing line by line in reading out charges accumulated in a photodiode serving as a photoelectric conversion element and resetting the charges accumulated in the photodiode.
As techniques employing the rolling shutter mode, for example, JP-A-2003-198948 discloses a solid-state imaging device and JP-A-2001-238138 discloses a timing generator for a solid-state imaging device.
In the solid-state imaging device disclosed in JP-A-2003-198948, V selecting means operates on the basis of a timing pulse from a timing generator, selects a row of a pixel unit, and outputs an address pulse (high level) to pixels belonging to the selected row at timing T1. The address pulse is supplied to address gates in the respective pixels and, as a result, the address gates are turned on, and amplifying transistors are connected to a vertical signal line. The V selecting means outputs a reset pulse at timing T2, whereby reset gates are turned on, FDs (photodiode) units are connected to a power supply Vdd, and charges (electrons) accumulated in the FD units are rejected. The V selecting means selects a select row, a first shutter row, and a second shutter row and drives pixel wirings corresponding thereto. For example, with five-hundred rows set from the first shutter row to the second shutter row and five rows set from the second shutter row to the select row, the V selecting means combines a high-luminance output signal and a low-luminance output signal outputted from an output unit to create a wide-dynamic range image.
The timing generator for the solid-state imaging device disclosed in JP-A-2001-238138 includes V and H counters that execute count operations with pulses of respective vertical synchronization signals VD and horizontal synchronization signals HD as triggers, a ROM for storing time series data representing a repetition pattern at a logical level of an output pulse, a ROM for storing edge data indicating at which count values of the V and H counters a logical level of a control pulse should transition, V and H comparators for transitioning the logical level of the control pulse at a point when the count values of the V and H counters coincide with the edge data and outputting, as a timing pulse, a result of a logical operation of the output pulse based on the time series data and the control pulse, and a combination logic circuit. The timing generator makes it possible to realize thinning-out readout according processing for setting the counter values of the V and H counters or values obtained by subtraction processing as addresses on a selected line and adding an arbitrary value to the count values of the counters. The timing generator adopts the rolling shutter system for switching a scroll direction by switching use and nonuse of a subtraction circuit.
However, in the related art disclosed in JP-A-2003-198948, the rolling shutter system for selecting rows of the FD units, from which chargers are read out, while shifting the rows one by one using a shift register is used. Therefore, it is impossible to control special readout timing for quickly reading out charges from the FD units of a part of rows of the pixel units or reading out charges while skipping arbitrary several rows.
In the related art disclosed in JP-A-2001-238138, reset timing is not taken into account at all with respect to readout timing. Therefore, when the thinning-out readout is performed, it is likely that images with gradually changing exposure time are read out on an upper side and a lower side of a readout image. In the thinning-out readout, since specific pixels are repeatedly subjected to readout processing, it is impossible to realize interlace readout for reading out an entire screen row by row in a double data rate frame.